A. Field of the Invention
The present invention relates to a semiconductor device and semiconductor device manufacturing method.
B. Description of the Related Art
In recent years, in response to demands for a reduction in size and improvement in performance of power source instruments in the field of power electronics, efforts have been concentrated on improving performance with respect to increasing breakdown voltage, increasing current, reducing loss, increasing damage resistance, and increasing speed in power semiconductor devices. Further, a vertical MOS power device driven by a MOS gate (an insulated gate formed of a metal-oxide film-semiconductor) has been proposed as a power semiconductor device such that an increase in current and a reduction in loss are possible.
Two kinds of structure, a planar gate structure wherein a MOS gate is provided in a plate form on a semiconductor substrate and a trench gate structure wherein a MOS gate is embedded inside a trench formed in a semiconductor substrate, are widely known as MOS gate structures of this MOS power device. For recent vertical power devices, attention is being focused on the trench gate structure, as it is structurally easy to obtain low on-state resistance characteristics.
A device has been proposed as a vertical MOS power device with a trench gate structure in which a p-type channel region and n-type semiconductor substrate are disposed so that the surfaces thereof are alternately exposed in a longitudinal direction between parallel trenches, and the surface form of an n+ type emitter region selectively formed in a surface layer of the p-type channel region is wide on the trench side and narrower on a central side between the trenches (for example, refer to JP-A-2008-034794).
Also, a device has been proposed as a vertical MOS power device with a trench gate structure in which differing first conductivity type semiconductor regions separated between first conductivity type base regions formed between parallel grooves, in contact at a side surface with both of neighboring parallel grooves and positioned between the same parallel grooves, are disposed with priority between parallel grooves near a peripheral structural portion, and are in conductive contact with an emitter electrode film (for example, refer to JP-A-2007-221012).
An example of a structure of the vertical MOS power devices with trench gate structures disclosed in JP-A-2008-034794 and JP-A-2007-221012 is shown in FIGS. 26 and 27. FIG. 26 is a sectional view showing a configuration of a heretofore known vertical semiconductor device with a trench gate structure. FIG. 27 is a plan view showing an enlargement of a planar structure of a cell portion of the vertical semiconductor device of FIG. 26. FIGS. 26 and 27 each are a vertical semiconductor device with a trench gate structure shown in FIGS. 9 and 13 of JP-A-2008-034794. A cell portion is an element portion that is a smallest functional unit.
As shown in FIGS. 26 and 27, trenches 102 are provided at predetermined intervals in the front surface of an n− type semiconductor substrate forming n− type drift region 101 in the heretofore known vertical semiconductor device with a trench gate structure. Trenches 102 are disposed in a stripe form extending in a direction (hereafter referred to as the longitudinal direction) perpendicular to the direction (hereafter referred to as the lateral direction) in which trenches 102 are aligned. A MOS gate formed of gate dielectric 103 and gate electrode 104 is embedded inside trench 102.
P-type channel regions 105 are selectively (hereafter taken to be an insular form) disposed in the longitudinal direction of trench 102 between neighboring trenches 102. Because of this, p-type channel region 105 and n− type drift region 101 are alternately exposed on the front surface of the n− type semiconductor substrate. N+ type emitter region 106 and p+ type body region 107 are selectively provided inside p-type channel region 105.
Emitter electrode 109 is in contact with n+ type emitter region 106 and p+ type body region 107 via a contact hole (not shown). N+ type buffer layer 110 and p+ type collector layer 111 are provided on the back surface of the n-type semiconductor substrate. Collector electrode 113 is in contact with p+ type collector layer 111. An IGBT with this kind of structure is such that it is possible to realize an increase in turn-off resistance and an increase in current density.
A reverse conducting IGBT (RC-IGBT) formed of an insulated gate bipolar transistor (IGBT) and freewheeling diode (FWD) formed on the same semiconductor substrate is publicly known as a power semiconductor device used at a high current density. A device has been proposed as a heretofore known RC-IGBT whose base layer is divided by an insulated gate trench, and which is formed by a spacer channel IGBT, formed by a configuration of a body region connected to an emitter electrode and a floating region not connected to the emitter electrode, and a diode connected in anti-parallel to the IGBT being formed on the same semiconductor substrate, wherein an IGBT cell region is formed of a unit cell region and a boundary cell region neighboring a diode cell region, and the interval between neighboring insulated gate trenches in the boundary cell region is short in comparison with the interval between insulated gate trenches configuring a floating region in a unit cell region (for example, refer to JP-A-2009-021557).
A reverse conducting semiconductor device wherein an IGBT element region and a diode element region exist together on the same semiconductor substrate, and the length by which a second trench gate electrode of the diode element region protrudes from an anode layer is greater than the length by which a first trench gate electrode of the IGBT element region protrudes from a body layer, has been proposed as another heretofore known RC-IGBT (for example, refer to JP-A-2009-170670).
The following device has been proposed as another heretofore known RC-IGBT. The structure is such that an emitter layer is provided in a first region on a first main surface side of a semiconductor substrate, while no emitter layer is provided in a second region. Also, the structure is such that a collector p-type layer is provided in the first region on a second main surface side of the semiconductor substrate, while a cathode n-type layer is provided in the second region. That is, the structure is such that an IGBT is configured in the first region, while a diode is configured in the second region. The impurity concentration of a p-type base layer of the second region is lower than the impurity concentration of a p-type base layer provided in the first region (for example, refer to JP-A-2008-053648).
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.